LA_TABLE Register (0x18000-0x18FFC) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

The following table shows the parameters relating to each layer of the code.

Table 1. LA_TABLE Register
Bit Access Type Description
15:8 R/W Number of cycles to wait at start of layer to enforce data dependences. Parameter set by the Vivado® IDE for the given code definition.
7 R/W Employed when circulant weight is greater than 1 in a decode operation. Parameter set by the Vivado IDE for the given code definition.
6:0 R/W Number of cycles per layer minus 1. Parameter set by the Vivado IDE for the given code definition. Depends upon packing factor (and so associated PSIZE).
  1. Read only possible while core is inactive (ACTIVE=0).
  2. The default value is undefined.