LDPC Block Interleaving - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

An LDPC code might contain inter-layer dependencies that can restrict the decoder (and encoder) from achieving peak throughput. These dependencies manifest as clock cycles where the decoder is idle. To hide the idle cycles, the decoder interleaves code blocks.

The interleaving algorithm determines whether to interleave another block based on observing idle clock cycles. This is qualified by there being sufficient memory to hold another code block, and the max_schedule parameter. The algorithm does not schedule a further block if the resulting number of interleaved blocks exceeds the max_schedule value. If no idle cycles are observed, no further blocks are interleaved.

The max_schedule parameter range is 0 to 3. When set to 0 (the default), the decoder might schedule up to a maximum of four blocks. The max_schedule value used by the scheduling algorithm is the lowest non-zero value defined for the active LDPC codes (that is, the LDPC codes associated with the blocks currently "in flight").

An increase in latency can be a consequence of filling all the idle cycles. Setting a lower max_schedule value provides a mechanism to limit interleaving with a potential reduction in latency as a result, but this depends on the characteristics of the LDPC code.