LDPC Code Memory Error Detection and Correction - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

LDPC code parameters, REF, and shared tables are stored in memories with Error Correction Code (ECC). This memory has the ability to detect two errors, and correct one error. For each memory, two error flags are generated and made available through the interrupt service register in order to monitor errors:

  • ECC error: normally 0, set when one or more errors have been detected in a word read from the respective memory.
  • ECC two-bit error: normally 0, set when 2 errors are detected in a word read from the respective memory. It might also be set when the number of errors in a word is greater than 2; however, this is not guaranteed.