LDPC codes are programmable through an AXI4-Lite interface. A class of Quasi-Cyclic (QC) codes are supported. The following figure elaborates the code parameterization and the following table summarizes the flexibility.
The checknode degree (DC) and variable node degree (DV) are counts of the number of 1s in each row and column respectively of the H matrix. For the respective base matrix, if sub-matrices have circulant weight greater than one, then DC and DV are counts of the total number of circulants in a layer or column respectively.
| Parameter | Range | Comment |
|---|---|---|
| Number of codes | 128 codes | Programmable (concurrently with operation to allow run-time code update). |
| Code base matrix definition in terms of circulants (QC) | 8,192 entries over all codes | Arbitrary apportionment over codes. Sufficient for 32 codes with P=128, N=8,192 and DV=4 (entries per code=DV*N/P=256). |
| Check node degree, DC | 2 ≤ DC ≤ 128 | Programmable per layer of code. |
| Variable node degree, DV | 1 ≤ DV | Programmable per code (set indirectly). |
| Number of layers, NLAYERS | 1 ≤ NLAYERS ≤ 256 | Programmable per code. |
| Sub-matrix size, P | 2 ≤ P ≤ 512 | Programmable per code. |
| Circulant weight, W |
W ≤ 4 |
Programmable per sub-matrix. Further constraints are imposed on codes by the Vivado® IDE when W>1 or when configured as an encoder. |
| Code-word length, N 1 | 4 ≤ N ≤ 32768 and N ≤ 256 × P and N>K | Programmable per code, multiple of P. |
| Parity length, N-K | 2 ≤ N-K ≤ 32766 1 and N-K ≤ 256 × P | Programmable per code, multiple of P (range derived from min(P) and max(N)-min(P)). |
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The underlying hardware can process 128 elements of each circulant in one clock cycle. Therefore when P>128, each circulant is processed over MV = ceil(P/128) cycles (MV=1,2,3 or 4). When P≤64, the underlying hardware can process multiple circulants in a single cycle subject to memory access conflicts associated with the code. The code limits, in particular, maximum DC, depend on packing. The Vivado Integrated Design Environment (IDE) automatically performs packing where possible, and checks the legality of a custom code definition. The SD-FEC C model also does this.
The following constraints are imposed by internal memory limitations:
- DC × MV ≤ 256
- NLAYERS × MV ≤ 256
- sum(DC) × MV ≤ 1024 for decode
- sum(DC) ≤ 2044 for encode
- (N ⁄ PSIZE) × MV ≤ 256 for encode
A normalized min-sum algorithm is used, and the normalization factor applied on each layer can be specified along with the other code parameters using the LDPC code definition file.