LDPC Code Parameters - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Important: Do not update the LDPC code parameters in 5G mode.

The LDPC code parameters can be written at any time; however registers should not be written that are associated with a code which is being processed by the engine (otherwise the behavior is unpredictable, and lockup might result, requiring a reset). The LDPC code parameters can only be read while the core is not active (ACTIVE=0); otherwise 0 is returned. Settings for the LDPC code parameters and shared tables are provided in the Vivado® IDE core configuration for a particular code definition. These registers must be provided for each code where the code register is derived using CODE, which takes a value 0 to 127. The code definition to be used is supplied for a block through the CTRL interface.