Normalization - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

The LDPC Decoder implements a normalized min-sum algorithm whereby the contributions of each layer to the soft output are normalized by a scale factor. In 5G mode, the normalization factor can be specified per block on the sc_idx field of CTRL. In non-5G NR mode, the scale factor can be specified for each layer of a code using the SC_TABLE register. A default scaling factor of 0.75 is set by the Vivado® IDE; however, the optimum scaling factor depends on the LDPC code, and this should be established within the context of the system. This is particularly important for low-rate codes with high variable-node degrees.

It is assumed that the LLR input has been symmetrically saturated to 6 bits as summarized in the Soft Value Input table (link below). If this is not done, there can be significant performance degradation. In this table, it is also suggested that the LLR is scaled to two fractional bits. However, LLR scaling is critical to performance and should be tuned within the context of the system to achieve optimal performance.