ORDER Register (0x18) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. ORDER Register
Bit Default Value Access Type Description
0 0 R/W Specifies whether the order of blocks can change from input to output
  • 0: Maintain order
  • 1: Out-of-order
  1. This register should only be changed when the core is not active (ACTIVE is 0).