Parameters should be carefully managed due to the wide variety
of modes that are supported by the SD-FEC
core. For 5G NR and initialized non-5G, the support logic takes control of the shared
LDPC code parameters; therefore these parameters must not be, under any circumstances,
written from the exposed AXI4-Lite interface provided.
For 5G NR, the support logic also assumes that the AXI_WR_PROTECT and CODE_WR_PROTECT
registers are writeable and CTRL and STATUS interfaces are enabled in the AXI_ENABLE register. If
the interfaces are disabled after the first CTRL data is applied, the
behavior is unpredictable. All other interfaces are disabled after reset and should be
enabled prior to using the core.
In all other modes, all SD-FEC core interfaces are disabled from reset. This allows the opportunity to configure parameters (such as LDPC codes) prior to the interfaces being enabled. WR_PROTECT can then be enabled to prevent registers being changed during operation. If it is necessary to change codes during operation, it is recommended that an external circuit be used to prevent changing of codes that are in use, as the behavior of the core in this circumstance is undefined.
It is also possible to stop operation of the decoder by disabling the CTRL interface, and monitoring the ACTIVE register. Codes
can then be changed without any risk of them being used. When code download is complete,
the CTRL interface can be re-enabled.