The parameter bus is an AXI4-Lite
memory-mapped slave
interface. The parameter bus uses the s_axi_aclk clock.
The AXI4-Lite interface is present when Parameter_Interface is not set to Initialized.
The parameter bus allows two outstanding transactions on the write interface, and one outstanding transaction on the read interface. The higher number of outstanding transactions on the write interface improves the write download throughput, allowing an LDPC code to be updated more quickly.
| Port | I/O |
|---|---|
| s_axi_aclk | I |
| s_axi_awaddr[17:0] | I |
| s_axi_awvalid | I |
| s_axi_awready | O |
| s_axi_wdata[31:0] | I |
| s_axi_wvalid | I |
| s_axi_wready | O |
| s_axi_bready | I |
| s_axi_bvalid | O |
| s_axi_araddr[17:0] | I |
| s_axi_arvalid | I |
| s_axi_arready | O |
| s_axi_rready | I |
| s_axi_rdata[31:0] | O |
| s_axi_rvalid | O |