Parameters - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

The hardware design supports the configuration parameters in the following table. These are set by the example application.

Table 1. Example Design Parameters
Parameter Description
Non-5G NR Control
Code Selects the LDPC code ID to be used or the turbo decode block size
5G Control 1
z_j Lifting factor
z_set Base graph cyclic shift set
bg Base graph
mb Number of parity bits
sc_idx Scale factor index, only available when the Normalized Min-Sum algorithm has been specified.
Common Control
max_iter Specifies the maximum decode iterations
term_on_pass Specifies that decode should terminate on parity pass.
BER
num_blocks Specifies the number of codeblocks to run through the data path.
snr Specifies the AWGN signal-to-noise ratio (SNR), -12dB to 16dB quantized to Fix17_11.
mod_type Modulation type:
  • 0 = BPSK
  • 1 = QPSK
  • 2 = QAM16
  • 3 = QAM64
zero_data Specifies that the source data should be all zeros, rather than randomized data. Note, when the encoder instance has not been included in the design it always uses zero data.
skip_channel Specifies that no channel noise should be applied.
  1. See Control Input Bus Ports for more details.