Product Specification - 1.1 English

A block diagram of the SD-FEC Integrated Block is shown in the following figure, which includes the high speed clock (667 MHz) domain and the Clock Domain Crossing (CDC) blocks. Optional Support logic is provided around the SD-FEC block to configure it; for 5G NR the optional logic provides support for both initialization and run-time configuration and for non-5G NR it provides support for initialization only. The optional support logic is generated using the Vivado® Integrated Design Environment. The optional support logic and SD-FEC block are referred to as the SD-FEC core.

Figure 1. SD-FEC Core Interfaces

The core uses AXI4 interfaces. A single AXI4-Lite memory mapped bus is used for parameters, such as LDPC code definitions, that persist for more than one block, and AXI4-Stream interfaces are used to provide data on a sample-by-sample basis (for example, DIN), or block-by-block basis (for example, CTRL). These interfaces provide handshake signals in addition to data. Further details are given in the AXI4-Stream Interface section. Data input and output buffers provide some scope to overlap input and output with encoder/decoder operation.

As shown in the previous figure, the internals of the SD-FEC core operate off a high speed clock, whereas the interfaces have their own clocks for ease of integration. Clock Domain Crossing (CDC) is provided on all interfaces and the data interfaces include width conversion to maintain high bandwidth with lower interface clock frequency. Specifically, the high speed clock domain has a 128-bit data interface capable of carrying up to 16 8-bit LLRs per clock cycle of the core, but the block has a 512-bit data interface, which allows up to four 128-bit samples to be time division multiplexed onto the core interface. This number can be configured to 1, 2, or 4 (using the AXI4-Lite interface), and if configured to 4, for example, it allows the interface clock rate to be reduced by a factor of four relative to the core clock while maintaining maximum bandwidth.