REG1 Register (0x2004+CODE*0x10) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID: PG256
Release Date: 2022-10-19
Version: 1.1 English

Table 1. REG1 Register
Bit	Access Type	Description
19:11	R/W	NM: Specifies internal soft-data memory requirements of codeword. Parameter set by the Vivado® IDE for the given code definition.
10	R/W	NO_PACKING: Determines whether multiple QC operations should be performed in the same clock cycle. 0: Pack multiple QC operations when P allows. 1: Do not pack multiple QC operations. If Packing is not enabled in the Vivado IDE, then NO_PACKING is internally overridden to be 1.
9:0	R/W	P: Size of sub-matrix Range: 2 ≤ P ≤ 512
See Non-5G Control Interface Definition for LDPC Decode and Encode for CODE definition. Setting invalid parameter values results in incorrect operation, requiring a reset to recover. The default value is undefined.