REG2 Register (0x2008+CODE*0x10) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. REG2 Register
Bit Access Type Description
23:24 R/W

MAX_SCHEDULE: Maximum number of blocks that can be interleaved by the LDPC encoder or decoder while code is active.

  • Range: 0 ≤ MAX_SCHEDULE ≤ 3.
  • 0 = Default scheduling behavior.

See LDPC Block Interleaving for details.

22 R/W

NO_FINAL_PARITY_CHECK: For decode, a parity check can be performed on the result when the specified maximum iterations is reached to establish if the final iteration resulted in a pass or fail. Adds some latency to the status output (data output can be obtained as soon as decode completed).

  • 0: Perform final parity check
  • 1: Do not perform final parity check. If the output parity check is disabled in the Vivado® IDE, then NO_FINAL_PARITY_CHECK is internally overridden to be 0.
21 R/W SPECIAL_QC: Required when circulant weight is greater than 1 in a decode operation. Parameter set by the Vivado IDE for the given code definition.
20 R/W

NORM_TYPE: Normalization required

  • 0: Normalize by 1
  • 1: Row normalization

See LDPC Code Support for details.

19:9 R/W NMQC: Specifies internal soft-data memory requirements of codeword. Parameter set by the Vivado IDE for the given code definition.
8:0 R/W

NLAYERS: Number of layers in code

Range: 1 ≤ NLAYERS ≤ 256

  1. See Non-5G Control Interface Definition for LDPC Decode and Encode for CODE definition.
  2. Setting invalid parameter values results in incorrect operation, requiring a reset to recover.
  3. The default value is undefined.