REG3 Register (0x200C+CODE*0x10) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English
Table 1. REG3 Register
Bit Access Type Description
26:16 R/W QC_OFF: QC_TABLE entry offset. QC_TABLE offset address= QC_OFF*16.
15:8 R/W LA_OFF: LA_TABLE entry offset. LA_TABLE offset address= LA_OFF*16.
7:0 R/W SC_OFF: SC_TABLE entry offset. SC_TABLE offset byte address = SC_OFF*4.
  1. See Non-5G Control Interface Definition for LDPC Decode and Encode for CODE definition.
  2. Setting invalid parameter values results in incorrect operation, requiring a reset to recover.
  3. The default value is undefined.