Important: Registers should be
programmed through a device driver (this generates correct values from simple
definitions of LDPC codes). The driver is provided by Xilinx.
The register map consists of the following types of parameters:
- Core Parameters (common to all codes)
- Turbo Code Parameters
- LDPC Code Parameters (per code)
- Shared LDPC Code Parameters
All registers start on 32-bit word aligned addresses. The two LSBs of the read and write addresses are assumed to be zero. Register read write access restrictions are summarized in the following sections. Further details of how code parameters might be managed are provided under Parameter Management.
| Address (Hex) | Register Name |
|---|---|
| Core Parameters | |
| 0x00 | AXI_WR_PROTECT Register |
| 0x04 | CODE_WR_PROTECT Register |
| 0x08 | ACTIVE Register |
| 0x0C | AXIS_WIDTH Register |
| 0x10 | AXIS_ENABLE Register |
| 0x14 | FEC_CODE Register |
| 0x18 | ORDER Register |
| 0x1C | Interrupt Status Register (ISR) |
| 0x20 | Interrupt Enable Register (IER) |
| 0x24 | Interrupt Disable Register (IDR) |
| 0x28 | Interrupt Mask Register (IMR) |
| 0x2C | ECC Interrupt Status Register |
| 0x30 | ECC Interrupt Enable Register |
| 0x34 | ECC Interrupt Disable Register |
| 0x38 | ECC Interrupt Mask Register |
| 0x3C | BYPASS Register |
| Turbo Code Parameters | |
| 0x100 | Turbo Code Register |
| LDPC Code Parameters | |
| 0x2000+CODE*0x10 | REG0 Register |
| 0x2004+CODE*0x10 | REG1 Register |
| 0x2008+CODE*0x10 | REG2 Register |
| 0x200C+CODE*0x10 | REG3 Register |
| Shared LDPC Code Parameters | |
| 0x10000–0x103FC | SC_TABLE Register |
| 0x18000–0x18FFC | LA_TABLE Register |
| 0x20000–0x27FFC | QC_TABLE Register |