Resets - 1.1 English

A single active-Low reset signal, reset_n, is used to reset the core and its interfaces. Reset is applied asynchronously, and internal synchronizers ensure that the reset is deasserted synchronously in each domain. A reset is required after power-up.The application of reset causes the core parameter and the turbo core parameter registers to take their reset value (LDPC and Shared LDPC code parameters are undefined). In-flight blocks are discarded, and the core becomes inactive, with the interfaces synchronously entering their disabled state (AXIS_ENABLE is zero).

The core comes out of reset with the AXI4-Stream interfaces disabled, allowing the interface width to be changed and code parameters to be written over the AXI4-Lite interface before operation begins. The final write can enable the interfaces to commence operation.

When the 5G NR standard is selected in the Vivado IDE, additional PL resources are used. The additional logic, which includes multiple clock domains and associated crossing logic, necessitates that reset_n be asserted for an extended number of clock cycles to ensure the block is fully reset. reset_n should be asserted for a minimum of:

Where T_clock is the period for the associated clock.

This is a suggested minimum, but because of the uncertainty associated with the clock domain crossings a further extension to the reset_n period may be required.