- Interface
- Specifies the S_AXI parameter interface configuration.
- Runtime-Configured
- the S_AXI parameter interface is exposed and the core and LDPC
parameters must be configured by an external source. The IP core
generates configuration parameters which are written to a file
and also exported to the standalone driver in the
Vitis™
software platform.
- Initialized retain I/F
-
The code
parameters are automatically initialized at device
configuration or after reset.
Initialization values for the core parameter can also be
specified using the corresponding core configuration screen
parameters.
- Initialized
- The S_AXI parameter interface is removed from the IP core and the Enable
I/Fs core parameter is set.
- Core Parameters
- Specifies initialization values for the following core
parameters when Interface is set to Initialized retain I/F or Initialized.
- Enable I/Fs
- Set all interfaces enable bits in the
AXIS_ENABLE register.
- Out of Order
- Sets the out of order bit in the ORDER
register.
- Interrupts
- Clears all bits of the Interrupt Mask register,
thereby enabling interrupts.
- ECC Interrupts
- None, Both, or Multi-bit Only.
- Both
- All bits of the ECC Interrupt Mask
register are cleared, enabling all ECC interrupts.
- Multi-bit Only
- Only the two-bit ECC error bits are
cleared, enabling only the two-bit ECC
interrupts.
- Bypass
- Sets the BYPASS register.
- AXI WR Protect
- Sets the AXI_WR_PROTECT register.
- Code WR Protect
- Sets the CORE_WR_PROTECT register.