Bit Width for Each AXIS_WIDTH.DOUT Setting | Field | Bits | Context | Range | Description | ||
---|---|---|---|---|---|---|---|
2 (4x) | 1 (2x) | 0 (1x) | |||||
512b | 256b | 128b | llr(0) | 7:0 | TURBO | -31.75 to 31.75 | Systematic LLR, two fractional bits |
LDPC | -31.75 to 31.75 | LLR, two fractional bits | |||||
llr(1) | 15:8 | TURBO | -31.75 to 31.75 | Parity LLR, two fractional bits | |||
LDPC | -31.75 to 31.75 | LLR, two fractional bits | |||||
llr(2) | 23:16 | TURBO | -31.75 to 31.75 | Parity Interleaved LLR, two fractional bits | |||
LDPC | -31.75 to 31.75 | LLR, two fractional bits | |||||
... | |||||||
llr(15) | 127:120 | ||||||
Unused | llr(16) | 135:128 | |||||
… | |||||||
llr(31) | 255:248 | ||||||
Unused | llr(32) | 263:256 | |||||
… | |||||||
llr(63) | 511:504 |