The example processor application is used to set up and control the BER test hardware and demonstrates how to configure the SD-FEC IP instance(s) using the low-level bare-metal driver.
The application files are output to the sw
directory within the example design project. A Tcl script to generate the example
application Vitis workspace project is also output during
example design generation, and placed in the project root directory. This can be
optionally run during example design generation by selecting the Build Vitis Project option of
the Example Design tab of the
Vivado®
IDE. The
script can be run manually using the
Xilinx®
software command line tool, xsct:
xsct -no-ini build_ps_example_app.tcl
When the design is built using a MicroBlaze™ processor, the generated application binary file (ELF file) can be imported into the example design project and used to simulate the whole system. The following Vivado Tcl commands import the generated ELF file into the example design project:
add_files -norecurse <ipinst>_ex.vitis/example_app/Release/example_app.elf
add_files -fileset sim_1 -norecurse <ipinst>_ex.vitis/example_app/Release/example_app.elf
set_property SCOPED_TO_REF ps_example [get_files -all-of_objects [get_fileset sources_1]
<ipinst>_ex.vitis/example_app/Release/example_app.elf]
set_property SCOPED_TO_CELLS { microblaze_ps } [get_files -all-of_objects [get_fileset
sources_1] <ipinst>.vitis/example_app/Release/example_app.elf]
set_property SCOPED_TO_REF ps_example [get_files -all-of_objects [get_fileset sim_1]
<ipinst>_ex.vitis/example_app/Release/example_app.elf]
set_property SCOPED_TO_CELLS { microblaze_ps } [get_files -all-of_objects [get_fileset
sim_1] <ipinst>_ex.vitis/example_app/Release/example_app.elf]
Note that if the Build Vitis Project option has been selected, these steps are done as part of the example design generation, and Vitis software platform workspaces are generated under <project_name>.vitis.