Status Output Ports (STATUS) - 1.1 English

Soft-Decision FEC Integrated Block LogiCORE IP Product Guide (PG256)

Document ID
PG256
Release Date
2022-10-19
Version
1.1 English

The status output bus (STATUS) is an AXI4-Stream master interface. The status output bus uses the m_axis_status_aclk clock. The status output provides information specific to each block. Its definition depends on whether 5G NR standard support is selected in the Vivado® IDE.

Table 1. Status Output Ports
Port I/O
m_axis_status_aclk I
m_axis_status_tvalid O
m_axis_status_tready I
m_axis_status_tdata[32/40] 1 O
  1. 40 bits if Standard is set to 5G, otherwise 32 bits.