Potential interrupt responses are summarized in the following table.
| Mode | PL Initialization Logic | SD-FEC | |||
|---|---|---|---|---|---|
| ECC 1-Bit (If Enabled) | ECC 2-Bit | ECC 1-bit (If Enabled) | ECC 2-Bit | Tlast Errors | |
| Initialized retain I/F (LDPC code initialization and AXI4-Lite interface present) | Inspect ECC ISR, bits 22 to 29 - Ignore or reconfigure PL | Inspect ECC ISR, bits 26 to 29 - reconfigure PL | Inspect ECC ISR, bits 0 to 21 - Ignore or reset | Inspect ECC ISR, bits 11 to 21 - Reset | Inspect ISR - Reset |
| Initialized (LDPC code initialized and AXI4-Lite interface not present) | Reconfigure PL | Reconfigure PL | Reconfigure PL | Reconfigure PL | Reconfigure PL |
| Runtime Configured (LDPC code not initialized and AXI4-Lite interface present) | N/A | N/A | Inspect ECC ISR, bits 0 to 21 - Ignore or reprogram codes when inactive | Inspect ECC ISR, bits 11 to 21 - Reset and reprogram codes | Inspect ISR - Reset and reprogram codes |