The subsystem clocks are described in Table: Subsystem Clocks .
The register interface also works on the s_axis_aclk core clock. Selection of s_axis_aclk is based on TxByteClkhs .
The s_axis_aclk should be selected such that the input bandwidth should be equal/greater than the output bandwidth. For example, s_axis_aclk*Pixel_width*Pixel_Mode = TxByteClk*No_Lanes*8 .
Note: If the above relations are not met, the MIPI CSI-2 TX controller will report an under-run condition.
Data Type |
Line Rate (Mbps) |
txByteclkhs (MHz) |
Lanes |
Pixel Mode |
s_axis_aclk (MHz) |
---|---|---|---|---|---|
RAW8 |
1200 |
150 |
1 |
1 |
150 |
RAW10 |
900 |
112.5 |
2 |
2 |
90 |
RAW12 |
1000 |
125 |
3 |
4 |
62.5 |
RGB888 |
800 |
100 |
4 |
4 |
33.33 |
RAW14 |
500 |
62.5 |
2 |
2 |
36 |
RGB565 |
1000 |
125 |
1 |
2 |
32 |
YUV-422-8 Bit |
1500 |
187.5 |
3 |
4 |
70.3125 |
Notes: 1. For data type interleaving with native video interface, select data types with similar pixel widths to avoid under-run or line buffer full. For example, RAW8, RAW10. |