The Configuration tab page provides core related configuration parameters.
Component Name: The Component Name is used as the name of the top-level wrapper file for the subsystem. The underlying netlist still retains its original name. Names must begin with a letter and must be composed from the following characters: a through z, 0 through 9, and “_”. The default is mipi_csi2_tx_subsystem_0.
Input Video Interface: Select the video interface used to accept pixel data. Values are AXI4S and Native.
Input Pixels per beat : Select the number of input pixels per clock on input interface. Values are 1 (single pixel), 2 (dual pixel), or 4(quad pixel).
Line Buffer Depth : Select the depth of internal RAM based on the bandwidth requirement such that the line buffer does not overflow. Values are 128, 256, 512, 1024, 2048, 4096, 8192, or 16384.
Note:
For IP generated by Vivado 2020.2 or earlier, the line buffer depth should be
greater than the line size in bytes *2 if the effective pixel width is less than or equal to 32. Otherwise, it should be greater than the line size in bytes *3.
For IP generated by Vivado 2021.1 or later, the line buffer depth should be the line size in bytes divided by 2.
CSI Lanes : Select the maximum number of D-PHY lanes for this subsystem instance. Values are 1, 2, 3, or 4.
Maximum Bits per Component: Select the maximum bit per component in a pixel. Values are 8, 10, 12, 14, 16, and 20.
CRC Generation Logic : When set, CRC computation is performed and appended to the payload data.
Enable Active Lanes : When set, the core supports the dynamic configuration of the number of active lanes from the maximum number of lanes selected during core generation using the parameter CSI Lanes . For example, when CSI Lanes is set to 3, the number of active lanes can be programmed using the protocol configuration register to be 1, 2, or 3. The core reports an error when the active lanes setting is greater than the serial lanes setting through the interrupt status register, bit 5.
Line Rate (Mb/s) : Based on the selected devices, enter a line rate value in megabits per second (Mbps) within the valid range: 80 to 3200 Mbps. The Vivado IDE automatically limits the line rates based on the selected device. For details about family/device specific line rate support, refer to the data sheet for your device.
Note: Based on the device selected, the Vivado IDE automatically limits the line rates. For details about family/device specific line rate support, refer to the specific data sheet.
Enable AXI4-Lite Register I/F : Select to enable the register interface for the MIPI D-PHY core.
Infer OBUFTDS for 7 series HS outputs : Select this option to infer OBUFTDS for HS outputs.
Note: This option is available only for 7 series D-PHY TX configuration. It is recommended to use this option for D-PHY compatible solution based on resistive circuit. For details, see D-PHY Solutions (XAPP894) [Ref 14] .
Enable Register Based Frame End Generation : When set, the core generates the frame end based on the register configuration (register offset 0x40 to 0x4C). Otherwise, the core generates the frame end implicitly based on the next frame start.
Enable Initial Deskew Transmission : When set, the core generates initial skew calibration packet.
Initial Skew calibration length (in txbyteclkhs) : Indicates the length of the Initial Skew calibration packet in number of Txbyteclkhs.
Enable Periodic Deskew Transmission : When set, the core generates periodic skew calibration packets.
Period skew packed length (in txbyteclkhs) : Indicates the length of the periodic Skew calibration packet in number of Txbyteclkhs.
Gap between periodic skew packets (In core clocks) : Indicates the frequency with which the periodic skew calibration packets will be sent, period between the two periodic packets should be given in number of core clocks.
Guarantees the Clock Rising Edge alignment to Payload Data on Serial Lines : This option is available for AMD Versal ™ device TX configuration when selected the first payload bit will be aligned to rising edge of the serial clock.