The Core Configuration register is described in Table: Core Configuration Register and allows you to enable and disable the MIPI CSI-2 TX Controller core and apply a soft reset during core operation.
|
Bits |
Name |
Reset Value |
Access |
Description |
|---|---|---|---|---|
|
31–5 |
Reserved |
N/A |
N/A |
Reserved Not used by the core Recommended to write 0 |
|
4 |
Clock Mode |
0x0 |
R/W |
Clock mode configuration 0: Continuous clock mode 1: Non-continuous clock mode |
|
3 |
ULPS Mode |
0x0 |
R/W |
Drives the lane into ULPS mode 0: Exit 1: Entry |
|
2 |
Controller Ready |
0x0 |
R |
Controller is ready for processing During soft-reset or core disable, rely on this status to ensure if the core has stopped all its activity 1: Controller is Ready 0: Controller is Inactive Note: The TX subsystem waits for the DPHY to complete its initialization, to indicate that the controller is ready. |
|
1 |
Soft Reset |
0x0 |
R/W |
Soft reset to core 1: Resets the ISR bits only 0: Takes the core out of soft reset Once the soft reset is released, core starts capturing new status information to ISR |
|
0 |
Core Enable |
0x0 |
R/W |
1: Enables the core to receive and process packets 0 (1) : Disables the core for operation • When disabled, the controller ends the current transfer by resetting all internal FIFOs and ISR • When enabled, the controller starts transferring the vsync packet (a new video frame) |
|
Notes: 1. When the Core is Disabled (Core Enable is set to 0), you can write into the registers, but the CSI2 TX Controller captures the value only after the core is Enabled (Core Enable is set to 1). The controller also ignores the writes to the Generic Short Packet Entry Register. |
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