• Support for 1 to 4 D-PHY lanes
• Maximum data rate of 3.2 Gbps for AMD Versal ™ adaptive SoCs and 2.5 Gbps for AMD UltraScale+™ devices
• Multiple data type support (RAW, RGB, YUV, User defined)
• Support for single, dual, quad pixel modes
• Support for 1 to 4 virtual channels
• Low power state (LP) insertion between the packets
• Ultra low power state (ULPS) mode generation using register access
• Interrupt generation to indicate subsystem status information
• AXI4-Lite interface for register access to configure different subsystem options
• Configurable Line Start/Line End packet generation
• Configurable selection of D-PHY register interface
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IP Facts Table |
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Subsystem Specifics |
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Supported Device Family (1) |
AMD Versal™ adaptive SoCs, AMD UltraScale+™ families, AMD Zynq™ UltraScale+ MPSoC, AMD Zynq™ 7000 SoC, AMD 7 series FPGAs |
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Supported User Interfaces |
AXI4-Lite, AXI4-Stream, Native Video |
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Resources |
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Provided with Subsystem |
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Design Files |
Encrypted RTL |
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Example Design |
Vivado IP Integrator |
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Test Bench |
Available |
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Constraints File |
XDC |
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Simulation Model |
Not Provided |
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Supported
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Standalone |
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Tested Design Flows (3) |
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Design Entry |
Vivado ™ Design Suite |
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Simulation |
For supported simulators, see the
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Synthesis |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 67896 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete list of supported devices, see the Vivado IP catalog. 2. Standalone driver details can be found in the Vitis directory (Vitis IDE > Help > Xilinx OS and Libraries Help > BSP and Libraries Document Collection (UG643)).
3.
For the supported versions of the tools, see the
4. For Example Design simulation needs to be run more than 1.5 ms because of MIPI initialization sequence. |
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