• Ensure MIPI DPHY and MIPI CSI-2 TX Controller cores are in the enable state by reading the registers.
• Ensure Incorrect Lane Configuration is not set in the MIPI CSI-2 TX Controller Interrupt status register.
• Ensure line buffer full condition is not set in the MIPI CSI-2 TX Controller Interrupt Status register.
Note: In case of line buffer full/under run conditions, check the input and output bandwidth ratios, see Clocking for details.
• Ensure Pixel Data Under-run is not set in the MIPI CSI-2 TX Controller Interrupt Status register.
• Ensure GSP FIFO Full is not set in the MIPI CSI-2 TX Controller Interrupt Status register.
Note: In case you encounter any errors, disable and re-enable the core to clear any stale data stored in the buffers.