Hardware Validation - 2.2 English

MIPI CSI-2 Transmitter Subsystem (PG260)

Document ID
PG260
Release Date
2023-05-16
Version
2.2 English

The MIPI CSI-2 TX Subsystem is tested in hardware for functionality, performance, and reliability using AMD Adaptive Computing evaluation platforms. The MIPI CSI-2 TX Subsystem verification test suites for all possible modules are continuously being updated to increase test coverage across the range of possible parameters for each individual module.

A series of MIPI CSI-2 TX Subsystem test scenarios are validated using the AMD development boards listed in Table: AMD Development Board . These boards permit the prototyping of system designs where the MIPI CSI-2 TX Subsystem processes the incoming image data into different short/long packets.

Table A-1: AMD Development Board

Target Family

Evaluation Board

Characterization Board

AMD Zynq UltraScale+™ MPSoC

ZCU102

N/A

AMD Versal™ AI Core Series

VCK190

N/A

AMD 7 series devices do not have a native MIPI IOB support. You will have to target the XPOI bank for Versal adaptive SoCs and HP bank I/O for UltraScale+ devices for MIPI IP implementation. For more information on MIPI IOB compliant solution and guidance, refer to D-PHY Solutions (XAPP894) [Ref 14] .