For AMD UltraScale+™ and AMD 7 series devices, the MIPI D-PHY core provides an I/O planner feature for I/O selection. You can select any I/O for the clock and data lanes in the TX core configuration for the selected HP I/O bank.
The MIPI D-PHY GUI does not have an I/O assignment tab for AMD Versal™ adaptive SoCs. Instead, you need to use consolidated I/O planning in the main Vivado IDE Planning that is a nibble planner. Select any I/O for the clock and data lanes in the TX core configuration for the selected XPIO bank.
Detailed steps on how to use the Vivado IDE Planning is detailed under section "I/O Planning for Versal Advanced IO Wizard" in Advanced I/O Wizard LogiCORE IP Product Guide (PG320) [Ref 16] .
Eight D-PHY IP cores can be implemented per I/O bank due to BITSLICE and BITSLICE_CONTROL instances in the UltraScale+ devices.
Note: The master and slave cores must be configured with the same line rate when sharing clkoutphy within I/O bank. The escape clock (txclkesc) configuration must also be the same.
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X-Ref Target - Figure 3-4 
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IMPORTANT: MIPI CSI-2 TX Subsystem and MIPI CSI-2 RX Subsystem can share clocking resources. In these cases, the MIPI CSI-2 TX Subsystem must be configured using the Include Shared Logic in Core option under the Shared Logic tab.
Note: The master and slave can be configured with a different line rate when sharing clkoutphy within an I/O bank when the following conditions are met:
1. When the line rate of the MIPI CSI-2 TX (master) is above 1500 Mbps, it must be connected to a MIPI CSI-2 RX with same line rate. The txbyteclkhs from the MIPI CSI-2 TX (master) core must be connected to the rxbyteclkhs_cnts_in in the MIPI CSI-2 RX (slave) core.
2. A MIPI CSI-2 TX (master) with a line rate of 1500 Mbps can be connected to a MIPI CSI-2 RX (slave) when the RX (slave) is configured for any line rate below 1500 Mbps.