Latency - 2.2 English

MIPI CSI-2 Transmitter Subsystem (PG260)

Document ID

PG260

Release Date

2023-05-16

Version

2.2 English

CSI2 TX Subsystem latency is defined as CSI2 TX Controller Latency + PHY Latency.

CSI2 TX Controller Latency: Time from the tlast (on AXIS interface) assertion to the rising edge of tx_requesths (PPI signal).

PHY Latency: tx_requesths (PPI signal) rising edge assertion to the HS-REQ on serial lines, i.e., LP-01 detection.

Table 2-1: MIPI CSI-2 TX Subsystem Latency
Data Type	MAX BPC	Pixel Mode	Line Buffer Depth	Lanes	Line Rate	s_axis_clk(Mhz)	Packet Length (in Bytes)	CSI2 TX Controller Latency (txbyteclkhs)	DPHY Latency (txbyteclkhs)	Subsystem Latency (Controller + DPHY) (txbyteclkhs)
RAW8	20	1	1024	1	1500	187.5	1920	21	4	25
RAW10	10	2	1024	2	1500	150	1920	19	4	23
RGB565	8	4	1024	4	1500	93.75	1920	502	4	506
RGB888	8	2	1024	4	1500	125	1920	21	4	265
RGB888	8	1	1024	4	1500	250	1920	17	4	21
YUV422	8	1	1024	3	1500	281	1920	19	4	23
YUV22-10	10	4	1024	4	1500	75	1920	746	4	750
YUV22-10	10	1	1024	4	1500	300	1920	18	4	22

Note: The table above is with AXI4-Stream interface, disabling the line start, line end packets, and continuous clock mode of PHY.