The MIPI CSI-2 TX Controller programming sequence is as follows. This Figure , This Figure , and This Figure show a graphical representation of the sequence:
1. Configure the registers and enable the core
a. Read the Core Configuration Register (Offset - 0x00) to ensure that the controller ready bit is set to 1 , before enabling the core anytime (for example, after reset or after disabling the core).
b. Configure the required configuration through register programming.
c. Enable the core and send video stream on input interface.
d. All along this sequence, either continuously poll or wait for external interrupt (if enabled) and read interrupt status register for any errors or status reported.
2. Disabling and re-enabling the core
° Disable the core using the Core Configuration Register (Offset - 0x00) (set the Core Enable bit to 0 ).
° Wait until the controller ready bit is set in the Core Configuration Register (Offset - 0x00) .
° Re-enable the core (set the Core Enable bit to 1 ).
3. ULPS Entry and ULPS Exit
° Drive the PHY Lanes to ULPS Mode, write 1 into the Core Configuration Register (Offset - 0x00) (set the ULPS Mode bit to 1 ).
° Corresponding PPI Signals are driven to the PHY ( txrequestesc , txulpsesc ) for the entry into the ULPS State.
° After the PHY Lanes have entered into the ULPS State ( ulpsactivenot goes low) the Interrupt Status register is updated with the corresponding status.
° Exit the ULPS state, write 0 into the Core Configuration Register (Offset - 0x00) (set the ULPS Mode bit to 0 ).
° Corresponding PPI Signal is driven to the PHY ( txulpsexit ) for exiting from the ULPS State.
° PPI deasserts the txrequestesc after a millisecond of deassertion of the ulpsactivenot signal. The ULPS exit is indicated through the Interrupt Status register.
° After 1 micro second, clear the ISR corresponding to Ulps. If you try to clear the ISR before 1 micro second, it shows the IP in ulps state only.
