Overview - 2.2 English

MIPI CSI-2 Transmitter Subsystem (PG260)

Document ID
PG260
Release Date
2023-05-16
Version
2.2 English

The top module instantiates all components of the core and example design that are needed for the design as shown in This Figure . This includes the MIPI CSI-2 TX Subsystem, MIPI CSI-2 RX Subsystem, V-TPG and ATG IP modules.

The example design can be generated for the two following configurations of MIPI CSI-2 TX and MIPI CSI-2 RX Subsystem:

1. Single Lane, RGB888 data type, Single Pixel Mode.

2. 4 Lanes, YUV422 8-bit data type, Quad Pixel Mode.

The example design can be used to perform a quick simulation of MIPI CSI-2 TX/RX Subsystems and to understand the interface behavior.

Figure 5-1: MIPI CSI2 TX Subsystem Example Design

X-Ref Target - Figure 5-1

X23014-MIPI_CSI2_TX_Subsystem_Example_Design.jpg

Note: The example design can be generated for the above-mentioned configurations only. The base IP GUI configuration is not considered to configure the MIPI CSI-2 TX Subsystems used in the example design.