Protocol Configuration Register (Offset - 0x04) - 2.2 English

31–16

Reserved

N/A

N/A

Reserved

Not used by the core

15

Line start/End Generation

0x0

R/W

Line synchronization packet generation

0: Do not generate line start/end

1: Generate line start/end

Note: Writing this bit might have an impact from the immediate received line, after the change in the configuration.

14-13

Pixel Mode

0x0 ⁽³⁾

R

Configured pixel mode

0x0—1 pixel mode

0x1—2 pixel mode

0x3—4 pixel mode

12-5

Reserved

N/A

N/A

Reserved

4–3

Maximum Lanes

Number of lanes configured during core generation

R

Maximum lanes of the core

0x0—1 Lane
0x1—2 Lanes
0x2—3 Lanes
0x3—4 Lanes

2

Reserved

N/A

Reserved

1–0

Active Lanes

Number of lanes configured during core generation

R/W

Configured lanes in the core ⁽¹⁾

0x0—1 Lane
0x1—2 Lanes
0x2—3 Lanes
0x3—4 Lanes

Notes:

1. When the Active Lanes option is disabled, the Maximum Lanes, and the Active Lanes register fields hold the same value.

2. If you want to change the active lanes, disable the core first and then modify the active lanes. Once the modification is done, enable the core.

3. Reset value is the Configured value in the GUI during the core generation.