Register Space - 2.2 English

MIPI CSI-2 Transmitter Subsystem (PG260)

Document ID
PG260
Release Date
2023-05-16
Version
2.2 English

This section details registers available in the MIPI CSI-2 TX Subsystem. The address map is split into following regions:

MIPI CSI-2 TX Controller core

MIPI D-PHY core

Each IP core is given an address space of 4K. The total address space given is 8K. Example offset addresses from the system base address when the MIPI D-PHY registers are enabled are shown in Table: Sub-Core Address Offsets .

Table 2-11: Sub-Core Address Offsets

IP Cores

Offset

MIPI CSI-2 TX Controller

0x0000

MIPI D-PHY

0x1000