The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
05/16/2023 |
2.2 |
• Updated the supported D-PHY specification version from 1.2 to 2.0. • Added a note about how the line buffer depth value is calculated in Configuration Tab . • Corrected calculation for YUV422 8-bit data type in Clocking . • Added a clarification about the line rate requirements for clocking resource sharing in I/O Planning . |
|
06/09/2022 |
2.2 |
• Updated Port Descriptions . • Updated Pixel Encoding section. • Updated Clocking section. • Updated Configuration Tab section. • Updated Latency section. |
|
06/30/2021 |
2.2 |
General updates. |
|
02/09/2021 |
2.2 |
Updated the document version to v2.2 on the title page. |
|
02/05/2021 |
2.2 |
General updates. |
|
07/14/2020 |
2.1 |
• Added support for AMD Versal ™ devices. |
|
06/24/2020 |
2.1 |
• Added support for RAW16 and RAW20. • Added support for equal bandwidth requirement for effective pixel width >=32. |
|
10/30/2019 |
2.1 |
Updated the core version to v2.1 |
|
07/02/2019 |
2.0 |
Added 2.5 Gbps support to the subsystem |
|
12/05/2018 |
2.0 |
• Updated Figures 3-3 and 3-4. • Updated Figure B-3 in Appendix B. • Updated the bandwidth requirement for effective pixel width <= 32. • Updated s_axis_aclk values in Table 3-2. |
|
04/04/2018 |
2.0 |
• Enhancement support for FE generation based on register configuration. • Updated the existing title ‘MIPI CSI-2 Transmit Subsystem v2.0’ to ‘MIPI CSI-2 Transmitter Subsystem v2.0’. |
|
10/04/2017 |
2.0 |
• MIPI D-PHY serial pins are grouped as an interface • Integrated DPHY initialization completion to assert Controller Ready. |
|
06/07/2017 |
1.0 |
Enhancement support for non-continuous clock mode |
|
04/05/2017 |
1.0 |
• MIPI D-PHY 3.1 changes integrated • Enhancement support for a case where the word count is greater than the payload received. |
|
10/05/2016 |
1.0 |
Initial release |