Shared Logic in the Core - 2.2 English

MIPI CSI-2 Transmitter Subsystem (PG260)

Document ID
PG260
Release Date
2023-05-16
Version
2.2 English

Selecting Shared Logic in the Core implements the subsystem with the MMCM and PLL inside the subsystem to generate all the clocking requirement of the PHY layer.

Select Include Shared Logic in Core if:

You do not require direct control over the MMCM and PLL generated clocks.

You want to manage multiple customizations of the subsystem for multi-subsystem designs.

This is the first MIPI CSI-2 TX Subsystem in a multi-subsystem system.

These components are included in the subsystem, and their output ports are also provided as subsystem outputs.

Note: Shared logic in a core configured subsystem must be active and running all the time if the clocks are shared by other CSI subsystem(s) in the system.