This chapter contains information about the test bench provided in the AMD Vivado ™ Design Suite.
The MIPI CSI-2 TX Subsystem delivers a demonstration test bench for the example design.
The test bench consists of the following modules:
• Device Under Test (DUT)
• Clock and reset generator
• Status monitor
The example design demonstration test bench is a simple Verilog module to exercise the example design and the core itself. It simulates an instance of the MIPI CSI-2 TX Subsystem that is externally looped back to the MIPI CSI-2 RX Subsystem. The MIPI CSI-2 TX Example Design test bench generates all the required clocks and resets.
• ATG-1 : The ATG-1 in init mode drives the VTPG to generate the required set of traffic based on configuration selected in XGUI.
• V-TPG : Receives input from ATG-1 and sends out the required traffic pattern to the Sub-set Converter.
• AXI Sub-set Converter : Performs the necessary pixel encoding followed by the MIPI CSI-2 TX controller and sends the traffic to MIPI CSI2 TX Subsystem.
• MIPI CSI-2 TX Subsystem : Packs the incoming pixel data to CSI-2 packets and sends it over DPHY interface for transmission.
• MIPI CSI-2 RX Subsystem : Receives the stream through MIPI CSI-2 TX/RX loopback and produces AXI4 video stream.
• ATG-2 : The ATG-2 in System Test Mode is used to check the Interrupt Status Register (ISR), data type and packet count register of CSI-2 RX Subsystem to determine Pass/Fail Results. If it fails to detect the expected information, it produces an error message.