Table: Vivado IDE Parameter to User Parameter Relationship shows the relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl Console).
Vivado IDE Parameter |
User Parameter |
Default Value |
---|---|---|
CSI Lanes |
C_CSI_LANES |
4 |
Maximum bits per component |
C_CSI_MAX_BPC |
14 |
Enable Active Lanes |
C_CSI_EN_ACTIVELANES |
0 |
Input Pixels per beat |
C_CSI_PIXEL_MODE |
1 |
Line Buffer Depth |
C_CSI_LINE_BUFR_DEPTH |
2048 |
CRC Generation Logic |
C_CSI_CRC_ENABLE |
1 |
Input Video Interface |
C_CSI_VID_INTERFACE |
AXI4_Stream |
Line Rate (Mb/s) |
C_HS_LINE_RATE |
1000 |
Enable AXI-4 Lite Register I/F |
C_DPHY_EN_REGIF |
0 |
Enable Register Based Frame End Generation |
C_EN_REG_BASED_FE_GEN |
0 |
Shared Logic |
SupportLevel |
0 |
Infer OBUFTDS for 7 series HS outputs |
C_EN_HS_OBUFTDS |
0 |
HP IO Bank Selection (1) |
HP_IO_BANK_SELECTION |
Value based on part selected. |
Clock Lane (1) |
CLK_LANE_IO_LOC |
Value based on part selected |
Data Lane0 (1) |
DATA_LANE0_IO_LOC |
Value based on part selected |
Data Lane1 (1) |
DATA_LANE1_IO_LOC |
Value based on part selected |
Data Lane2 (1) |
DATA_LANE2_IO_LOC |
Value based on part selected |
Data Lane3 (1) |
DATA_LANE3_IO_LOC |
Value based on part selected |
Enable Initial Deskew Transmission |
C_CSI_XMIT_INITIAL_DESKEW |
0 |
Length of Initial Skew calibration Packets(txbyteclkhs clocks) |
C_CSI_INIT_DESKEW_PATRN_LEN |
4096 |
Enable Periodic Deskew Transmission |
C_CSI_XMIT_PERIODIC_DESKEW |
0 |
Length of Periodic Skew calibration Packets(txbyteclkhs clocks) |
C_CSI_PERIODIC_PATRN_LEN |
4096 |
Time after which next periodic pattern has to be sent(In core clocks) |
C_CSI_PERIODIC_TIME |
50 |
Guarantees the Clock Rising Edge alignment to Payload Data on Serial Lines Note: For Versal devices only |
C_EN_CTS_TX |
False |
Notes: |