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Name of Protocol Check
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Protocol Support
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Description
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AXI_ERRM_AWADDR_BOUNDARY
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AXI4/AXI3
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A write burst cannot cross a 4 KB boundary.
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AXI_ERRM_AWADDR_WRAP_ALIGN
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AXI4/AXI3
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A write transaction with burst type WRAP has an aligned address.
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AXI_ERRM_AWBURST
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AXI4/AXI3
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A value of 2’b11 on AWBURST is not permitted when AWVALID is High.
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AXI_ERRM_AWLEN_LOCK
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AXI4/AXI3
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Exclusive access transactions cannot have a length greater than 16 beats.
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AXI_ERRM_AWCACHE
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AXI4/AXI3
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If not cacheable (AWCACHE[1] == 1'b0), AWCACHE = 2'b00.
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AXI_ERRM_AWLEN_FIXED
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AXI4/AXI3
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Transactions of burst type FIXED cannot have a length greater than 16 beats.
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AXI_ERRM_AWLEN_WRAP
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AXI4/AXI3
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A write transaction with burst type WRAP has a length of 2, 4, 8, or 16.
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AXI_ERRM_AWSIZE
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AXI4/AXI3
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The size of a write transfer does not exceed the width of the data interface.
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AXI_ERRM_AWVALID_RESET
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AXI4/AXI3/Lite
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AWVALID is Low for the first cycle after ARESETn goes High.
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AXI_ERRM_AWADDR_STABLE
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AXI4/AXI3/Lite
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Handshake Checks AWADDR must remain stable when AWVALID is asserted and AWREADY Low.
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AXI_ERRM_AWBURST_STABLE
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AXI4/AXI3
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Handshake Checks AWBURST must remain stable when AWVALID is asserted and AWREADY Low.
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AXI_ERRM_AWCACHE_STABLE
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AXI4/AXI3
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Handshake Checks AWCACHE must remain stable when AWVALID is asserted and AWREADY Low.
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AXI_ERRM_AWID_STABLE
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AXI4/AXI3
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Handshake Checks AWID must remain stable when AWVALID is asserted and AWREADY Low.
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AXI_ERRM_AWLEN_STABLE
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AXI4/AXI3
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Handshake Checks AWLEN must remain stable when AWVALID is asserted and AWREADY Low.
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AXI_ERRM_AWLOCK_STABLE
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AXI4/AXI3
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Handshake Checks AWLOCK must remain stable when AWVALID is asserted and AWREADY Low.
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AXI_ERRM_AWPROT_STABLE
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AXI4/AXI3/Lite
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Handshake Checks AWPROT must remain stable when AWVALID is asserted and AWREADY Low.
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AXI_ERRM_AWSIZE_STABLE
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AXI4/AXI3
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Handshake Checks AWSIZE must remain stable when AWVALID is asserted and AWREADY Low.
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AXI_ERRM_AWQOS_STABLE
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AXI4/AXI3
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Handshake Checks AWQOS must remain stable when AWVALID is asserted and AWREADY Low.
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AXI_ERRM_AWREGION_STABLE
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AXI4
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Handshake Checks AWREGION must remain stable when ARVALID is asserted and AWREADY Low.
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AXI_ERRM_AWVALID_STABLE
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AXI4/AXI3/Lite
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Handshake Checks Once AWVALID is asserted, it must remain asserted until AWREADY is High.
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AXI_RECS_AWREADY_MAX_WAIT
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AXI4/AXI3/Lite
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Recommended that AWREADY is asserted within MAXWAITS cycles of AWVALID being asserted.
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AXI_ERRM_WDATA_NUM
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AXI4/AXI3
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The number of write data items matches AWLEN for the corresponding address. This is triggered when any of the following occurs:
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Write data arrives and WLAST is set, and the WDATA count is not equal to AWLEN
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Write data arrives and WLAST is not set, and the WDATA count is equal to AWLEN
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ADDR arrives, WLAST is already received, and the WDATA count is not equal to AWLEN
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AXI_ERRM_WSTRB
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AXI4/AXI3/Lite
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Write strobes must only be asserted for the correct byte lanes as determined from the: Start Address, Transfer Size, and Beat Number.
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AXI_ERRM_WVALID_RESET
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AXI4/AXI3/Lite
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WVALID is Low for the first cycle after ARESETn goes High.
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AXI_ERRM_WDATA_STABLE
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AXI4/AXI3/Lite
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Handshake Checks WDATA must remain stable when WVALID is asserted and WREADY Low.
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AXI_ERRM_WLAST_STABLE
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AXI4/AXI3
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Handshake Checks WLAST must remain stable when WVALID is asserted and WREADY Low.
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AXI_ERRM_WSTRB_STABLE
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AXI4/AXI3/Lite
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Handshake Checks WSTRB must remain stable when WVALID is asserted and WREADY Low.
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AXI_ERRM_WVALID_STABLE
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AXI4/AXI3/Lite
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Handshake Checks Once WVALID is asserted, it must remain asserted until WREADY is High.
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AXI_RECS_WREADY_MAX_WAIT
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AXI4/AXI3/Lite
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Recommended that WREADY is asserted within MAXWAITS cycles of WVALID being asserted.
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AXI_ERRS_BRESP_WLAST
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AXI4/AXI3
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A slave must not take BVALID High until after the last write data is handshake is complete.
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AXI_ERRS_BRESP_EXOKAY
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AXI4/AXI3
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An EXOKAY write response can only be given to an exclusive write access.
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AXI_ERRS_BVALID_RESET
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AXI4/AXI3/Lite
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BVALID is Low for the first cycle after ARESETn goes High.
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AXI_ERRS_BRESP_AW
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AXI4/AXI3/Lite
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A slave must not take BVALID High until after the write address is handshake is complete.
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AXI_ERRS_BID_STABLE
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AXI4/AXI3
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Handshake Checks BID must remain stable when BVALID is asserted and BREADY Low.
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AXI_ERRS_BRESP_STABLE
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AXI4/AXI3/Lite
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Checks BRESP must remain stable when BVALID is asserted and BREADY Low.
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AXI_ERRS_BVALID_STABLE
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AXI4/AXI3/Lite
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Once BVALID is asserted, it must remain asserted until BREADY is High.
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AXI_RECM_BREADY_MAX_WAIT
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AXI4/AXI3/Lite
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Recommended that BREADY is asserted within MAXWAITS cycles of BVALID being asserted.
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AXI_ERRM_ARADDR_BOUNDARY
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AXI4/AXI3
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A read burst cannot cross a 4 KB boundary.
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AXI_ERRM_ARADDR_WRAP_ALIGN
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AXI4/AXI3
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A read transaction with a burst type of WRAP must have an aligned address.
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AXI_ERRM_ARBURST
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AXI4/AXI3
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A value of 2'b11 on ARBURST is not permitted when ARVALID is High.
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AXI_ERRM_ARLEN_LOCK
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AXI4/AXI3
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Exclusive access transactions cannot have a length greater than 16 beats.
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AXI_ERRM_ARCACHE
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AXI4/AXI3
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When ARVALID is High, if ARCACHE[1] is Low, then ARCACHE[3:2] must also be Low.
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AXI_ERRM_ARLEN_FIXED
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AXI4/AXI3
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Transactions of burst type FIXED cannot have a length greater than 16 beats.
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AXI_ERRM_ARLEN_WRAP
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AXI4/AXI3
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A read transaction with burst type of WRAP must have a length of 2, 4, 8, or 16.
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AXI_ERRM_ARSIZE
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AXI4/AXI3
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The size of a read transfer must not exceed the width of the data interface.
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AXI_ERRM_ARVALID_RESET
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AXI4/AXI3/Lite
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ARVALID is Low for the first cycle after ARESETn goes High.
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AXI_ERRM_ARADDR_STABLE
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AXI4/AXI3/Lite
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ARADDR must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRM_ARBURST_STABLE
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AXI4/AXI3
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ARBURST must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRM_ARCACHE_STABLE
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AXI4/AXI3
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ARCACHE must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRM_ARID_STABLE
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AXI4/AXI3
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ARID must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRM_ARLEN_STABLE
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AXI4/AXI3
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ARLEN must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRM_ARLOCK_STABLE
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AXI4/AXI3
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ARLOCK must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRM_ARPROT_STABLE
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AXI4/AXI3/Lite
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ARPROT must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRM_ARSIZE_STABLE
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AXI4/AXI3
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ARSIZE must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRM_ARQOS_STABLE
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AXI4/AXI3
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ARQOS must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRM_ARREGION_STABLE
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AXI4
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ARREGION must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRM_ARVALID_STABLE
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AXI4/AXI3/Lite
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Once ARVALID is asserted, it must remain asserted until ARREADY is High.
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AXI_RECS_ARREADY_MAX_WAIT
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AXI4/AXI3/Lite
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Recommended that ARREADY is asserted within MAXWAITS cycles of ARVALID being asserted.
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AXI_ERRS_RDATA_NUM
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AXI4/AXI3
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The number of read data items must match the corresponding ARLEN.
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AXI_ERRS_RID
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AXI4/AXI3
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The read data must always follow the address that it relates to. Therefore, a slave can only give read data with an ID to match an outstanding read transaction.
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AXI_ERRS_RRESP_EXOKAY
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AXI4/AXI3
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An EXOKAY read response can only be given to an exclusive read access.
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AXI_ERRS_RVALID_RESET
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AXI4/AXI3/Lite
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RVALID is Low for the first cycle after ARESETn goes High.
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AXI_ERRS_RDATA_STABLE
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AXI4/AXI3/Lite
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RDATA must remain stable when RVALID is asserted and RREADY Low.
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AXI_ERRS_RID_STABLE
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AXI4/AXI3
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RID must remain stable when RVALID is asserted and RREADY Low.
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AXI_ERRS_RLAST_STABLE
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AXI4/AXI3
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RLAST must remain stable when RVALID is asserted and RREADY Low.
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AXI_ERRS_RRESP_STABLE
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AXI4/AXI3/Lite
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RRESP must remain stable when RVALID is asserted and RREADY Low.
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AXI_ERRS_RVALID_STABLE
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AXI4/AXI3/Lite
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Once RVALID is asserted, it must remain asserted until RREADY is High.
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AXI_RECM_RREADY_MAX_WAIT
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AXI4/AXI3/Lite
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Recommended that RREADY is asserted within MAXWAITS cycles of RVALID being asserted.
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AXI_ERRM_EXCL_ALIGN
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AXI4/AXI3
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The address of an exclusive access is aligned to the total number of bytes in the transaction.
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AXI_ERRM_EXCL_LEN
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AXI4/AXI3
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The number of bytes to be transferred in an exclusive access burst is a power of 2, that is, 1, 2, 4, 8, 16, 32, 64, or 128 bytes.
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AXI_RECM_EXCL_MATCH
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AXI4/AXI3
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Recommended that the address, size, and length of an exclusive write with a given ID is the same as the address, size, and length of the preceding exclusive read with the same ID.
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AXI_ERRM_EXCL_MAX
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AXI4/AXI3
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128 is the maximum number of bytes that can be transferred in an exclusive burst.
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AXI_RECM_EXCL_PAIR
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AXI4/AXI3
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Recommended that every exclusive write has an earlier outstanding exclusive read with the same ID.
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AXI_ERRM_AWUSER_STABLE
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AXI4/AXI3
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AWUSER must remain stable when AWVALID is asserted and AWREADY Low.
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AXI_ERRM_WUSER_STABLE
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AXI4/AXI3
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WUSER must remain stable when WVALID is asserted and WREADY Low.
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AXI_ERRS_BUSER_STABLE
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AXI4/AXI3
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BUSER must remain stable when BVALID is asserted and BREADY Low.
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AXI_ERRM_ARUSER_STABLE
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AXI4/AXI3
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ARUSER must remain stable when ARVALID is asserted and ARREADY Low.
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AXI_ERRS_RUSER_STABLE
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AXI4/AXI3
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RUSER must remain stable when RVALID is asserted and RREADY Low.
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AXI_AUXM_RCAM_OVERFLOW
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AXI4/AXI3/Lite
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Read CAM overflow, increase MAXRBURSTS parameter.
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AXI_AUXM_RCAM_UNDERFLOW
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AXI4/AXI3/Lite
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Read CAM Underflow
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AXI_AUXM_WCAM_OVERFLOW
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AXI4/AXI3/Lite
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Write CAM overflow, increase MAXWBURSTS parameter.
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AXI_AUXM_WCAM_UNDERFLOW
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AXI4/AXI3/Lite
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Write CAM Underflow
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AXI_AUXM_EXCL_OVERFLOW
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AXI4/AXI3
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Exclusive access monitor overflow, increase EXMON_WIDTH parameter.
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AXI4LITE_ERRS_BRESP_EXOKAY
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Lite
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A slave must not give an EXOKAY response on an AXI4-Lite interface.
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AXI4LITE_ERRS_RRESP_EXOKAY
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Lite
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A slave must not give an EXOKAY response on an AXI4-Lite interface.
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AXI4LITE_AUXM_DATA_WIDTH
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Lite
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DATA_WIDTH parameter is 32 or 64.
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