This section includes information about using Xilinx ® tools to customize and generate the core in the Vivado Design Suite.
If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 5] for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
1. Select the IP from the Vivado IP catalog.
2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
Note: Figures in this chapter are an illustration of the Vivado Integrated Design Environment (IDE). The layout depicted here might vary from the current version.
This Figure shows the AXI VIP Vivado IDE Basic Settings tab configuration screen.
For the runtime parameter descriptions, see Table: AXI VIP User Parameters .
• Component Name – The component name is used as the base name of output files generated for the module. Names must begin with a letter and must be composed from characters: a to z, 0 to 9 and "_".
• Interface Mode – Controls the mode of protocol to be configured as master, slave, or pass-through.
• Protocol – Selects the specific AXI protocol.
• Read or Write Mode – Enables the AXI read or write mode.
• Address Width – Selects the address width. Default at 32.
• Data Width – Selects the data width. Default at 32.
• ID Width – Selects the ID width. Default at 0.
• User Signal Widths – Selects the width for each user signal. Default at 0.