Features - 1.1 English

AXI Verification IP LogiCORE IP Product Guide (PG267)

Document ID

PG267

Release Date

2021-12-02

Version

1.1 English

• Supports all protocol data widths, address widths, transfer types, and responses

• Transaction-level protocol checking (burst type, length, size, lock type, and cache type)

• Arm ^® -based protocol transaction level checker for tools that support assertion property [Ref 1]

• Behavioral SystemVerilog Syntax

• SystemVerilog class-based API

• Synthesizes to nets and constant tie-offs

LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family ⁽¹⁾	UltraScale+™, UltraScale™, Zynq ^® -7000 SoC, 7 series FPGAs
Supported User Interfaces	AXI4, AXI4-Lite, AXI3
Resources	N/A
Provided with Core
Design Files	SystemVerilog
Example Design	SystemVerilog
Test Bench	N/A
Constraints File	N/A
Simulation Model	Unencrypted SystemVerilog
Supported S/W Driver	N/A
Tested Design Flows ⁽²⁾ ⁽³⁾
Design Entry	Vivado ^® Design Suite
Simulation ⁽⁴⁾	For supported simulators, see the Xilinx Design Tools: Release Notes Guide .
Synthesis	Vivado Synthesis
Support
Release Notes and Known Issues	Master Answer Record: 68234
All Vivado IP Change Logs	Master Vivado IP Change Logs: 72775
Xilinx Support web page
Notes: 1. For a complete list of supported devices, see the Vivado IP catalog. 2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide . 3. This IP does not deliver VIP for Zynq PS. It only delivers the VIP core for AXI3, AXI4, and AXI4-Lite interfaces. 4. To take advantage of the full features of this IP, it requires simulators supporting advanced simulation capabilities. 5. The AXI VIP can only act as a protocol checker when contained within a VHDL hierarchy. 6. To use the virtual part of the AXI Verification IP, it must be in a Verilog hierarchy. 7. Do not import two different revisions/versions of the axi_vip packages. This causes elaboration failures. 8. All AXI VIP and parents to the AXI VIP must be upgraded to the latest version.