GEN_EVENTS/RAND_EVENTS – Assert and Remain Asserted for a Number of Events - 1.1 English

AXI Verification IP LogiCORE IP Product Guide (PG267)

Document ID
PG267
Release Date
2021-12-02
Version
1.1 English

When this policy is active, it drives the *READY signal 0 for low_time cycles and then drives 1 until event_count handshakes occur.

Note: There is a built-in watchdog that triggers after the event_cycle_count_reset cycles and the programmed number of events has not been satisfied. This terminates that part of the policy. The policy repeats until the channel is given a different policy.

The value of low_time can range from 0 to 256 cycles. The READY remains asserted for N channel accept events, where N can be from 1 to N beats. This allows you to assert a READY after some number of cycles and keep it asserted indefinitely or for some number of events.

When attempting to model a self-draining FIFO, an event cycle count time reset is provided. This allows you to configure the READY to be deasserted after some number of events, unless the event cycle count time has expired. In this case, the event count resets and the READY remains asserted for N more events.

This Figure shows that following event A, there is a delay of low_time ACLKs, then the READY is asserted. It remains asserted for events E1 to E4 then deasserts since the event count is satisfied. The algorithm then restarts at A.

Figure D-18: GEN_EVENTS/RAND_EVENTS

X-Ref Target - Figure D-18

X18600-axi-vip-gen-event.jpg