GEN_OSC/RAND_OSC – Assert and Remain Asserted for a Number of Cycles - 1.1 English

AXI Verification IP LogiCORE IP Product Guide (PG267)

Document ID
PG267
Release Date
2021-12-02
Version
1.1 English

When this policy is active, it drives the *READY signal 0 for low_time cycles and then drives 1 for high_time cycles.

Note: The *READY does not drop until the specified number of cycles has occurred. The policy repeats until the channel is given a different policy.

This Figure shows that following event A, there is a delay of low_time ACLKs, then READY is asserted. After high_time cycles of ACLK, READY is deasserted and the counter restarts at A.

Figure D-17: GEN_OSC/RAND_OSC

X-Ref Target - Figure D-17

X18601-axi-vip-gen-osc.jpg