The AMD LogiCORE™ AXI Verification IP (VIP) core is developed to support the simulation of customer designed AXI-based IP. The AXI VIP core supports three versions of the AXI protocol (AXI3, AXI4, and AXI4-Lite).
The AXI VIP is an unencrypted SystemVerilog source comprised of a SystemVerilog class library and synthesizable RTL.
The AXI VIP controls the embedded RTL interface through a virtual interface. AXI transactions are constructed in the customer's verification environment and passed to the AXI driver class. The driver class then manages the timing and drives the content on the interface.