Introduction - 1.1 English

AXI Verification IP LogiCORE IP Product Guide (PG267)

Document ID
PG267
Release Date
2021-12-02
Version
1.1 English

The Xilinx ® LogiCORE™ AXI Verification IP (VIP) core has been developed to support the simulation of customer designed AXI-based IP. The AXI VIP core supports three versions of the AXI protocol (AXI3, AXI4, and AXI4-Lite) .

The AXI VIP is unencrypted SystemVerilog source that is comprised of a SystemVerilog class library and synthesizable RTL.

The embedded RTL interface is controlled by the AXI VIP through a virtual interface. AXI transactions are constructed in the customer's verification environment and passed to the AXI driver class. The driver class then manages the timing and drives the content on the interface.