Multiple Simulation Sets - 1.1 English

AXI Verification IP LogiCORE IP Product Guide (PG267)

Document ID
PG267
Release Date
2021-12-02
Version
1.1 English

The Vivado Design Suite has a feature that each design can have multiple simulation sets according to your settings (AR: 64111 ). Especially, multiple test benches can be constructed for the same design. For example, one test bench provides stimulus for behavioral simulation of a complicated design and a different test bench provides stimulus for timing simulation of the implemented design.

The AXI VIP example design in the 2018.3 release has simulation sets listed in Table: Simulation Sets for AXI VIP . The sim_all_config is a comprehensive simulation set. See the AXI VIP Example Test Bench and Test section for a list of features. It shows different examples of how to use the AXI VIP in a complex method.

For ease of use, 10 additional simulation sets with simple codes are also included in the example design. Naming of these 10 simulation sets:

sim_<basic or adv>_mst_<mode>__pt_<mode>__slv_<mode>

Where mode = active, mem, passive, or combo.

For Master VIP, it can be in active or passive mode.

° In active mode, it generates transactions and sends it out.

° In passive mode, pass-through VIP is in run-time master mode while master VIP is not active.

For Slave VIP, it can be in mem, passive, or combo mode.

° In mem mode, it means slave VIP has a memory model.

° In passive mode, pass-through VIP is in run-time slave mode while slave VIP is not active.

° In combo mode, it means slave VIP does not have a memory model.

For Pass-through VIP, it can be in mst, slv, passive, or mem mode.

° In mst mode, pass-through VIP is in run-time master mode.

° In slv mode, pass-through VIP is in run-time slave mode without a memory model.

° In passive mode, pass-through VIP is not active.

° In mem mode, pass-through VIP is in run-time slave mode with a memory model.

For more information, see Table: Simulation Sets for AXI VIP .

For example, sim_basic_mst_passive__pt_mst__slv_comb means this simulation set is performing a basic feature of the AXI VIP when the AXI master VIP is in passive mode. The AXI pass-through VIP is in the runtime master mode and communicates to the AXI slave VIP which does not include the memory model.

For the 10 simulation set test benches, it includes three files which are generic_tb , master stimulus , and slave stimulus .

The generic_tb performs a simple self-checking of the master side (can be AXI master VIP or AXI pass-through VIP in runtime master mode) against the slave side (can be AXI slave VIP or AXI pass-through VIP in runtime slave mode).

Master stimulus is generated by the AXI master VIP or AXI pass-through VIP in the runtime master mode.

Slave stimulus is generated by the AXI slave VIP or AXI pass-through VIP in the runtime slave mode with/without the memory model. The slave mem stimulus file is included and you can access the file to check the AXI slave VIP with the memory model.

The difference between basic and advanced simulation sets is that the basic simulation set shows the code snippets which are needed in the test bench to use the AXI VIP . Advanced simulation set adds more APIs such as user-configured READY signals which are optional. For more information, see the example design in the Vivado Design Suite and for usage of APIs, see the AXI VIP API Documentation [Ref 12] .

The following shows how to generate a transaction for each mode:

1. To generate a transaction for the AXI master VIP, see the mst_stimulus.sv from any of the 10 simulation sets in Table: Simulation Sets for AXI VIP .

2. To generate a transaction response for a basic AXI slave VIP, see the slv_basic_stimulus.sv from any of the 10 simulation sets in Table: Simulation Sets for AXI VIP . For memory model requirements, see the mem_basic_stimulus.sv .

3. To generate a transaction response for an advanced AXI slave VIP, see the slv_stimulus.sv from any of the 10 simulation sets in Table: Simulation Sets for AXI VIP . For memory model requirements, see the mem_stimulus.sv .

4. To generate a transaction for the AXI pass-through VIP, see the passthrough_mst_stimulus.sv from any of the simulation sets in Table: Simulation Sets for AXI VIP .

5. To generate a transaction response for a basic AXI pass-through VIP, see the passthrough_slv_basic_stimulus.sv from any of the simulation sets in Table: Simulation Sets for AXI VIP . For memory model requirements, see the passthrough_mem_basic_stimulus.sv .

6. To generate a transaction response for an advanced AXI pass-through VIP, see the passthrough_slv_stimulus.sv from any of the simulation sets in Table: Simulation Sets for AXI VIP . For memory model requirements, see the passthrough_mem_stimulus.sv .

7. When you open the AXI VIP example design under the Sources window, it shows 11 simulation sets. You can choose any simulation sets and run simulation or view the source codes of each test bench.

Table 6-1: Simulation Sets for AXI VIP

Simulation Set Name

Files Included

Description

sim_basic_mst_passive_pt_mst_slv_comb

passthrough_mst_stimulus.sv

slv_basic_stimulus.sv

generic_tb.sv

Basic feature of AXI VIP when AXI master VIP is in passive mode. AXI pass-through VIP is in runtime master mode and talks to AXI slave VIP which does not include memory model.

sim_basic_mst_active_pt_slv_slv_passive

mst_stimulus.sv

passthrough_slv_basic_
stimulus.sv

generic_tb.sv

Basic feature of AXI VIP when AXI master VIP is in active mode. AXI pass-through VIP is in runtime slave mode without memory model. AXI slave VIP is in passive mode.

sim_basic_mst_active_pt_mem_slv_passive

mst_stimulus.sv

passthrough_mem_basic_
stimulus.sv

generic_tb.sv

Basic feature of AXI VIP when AXI master VIP is in active mode. AXI pass-through VIP is in runtime slave mode with memory model. AXI slave VIP in passive mode.

sim_basic_mst_active_pt_passive_slv_mem

mst_stimulus.sv

mem_basic_stimulus.sv

generic_tb.sv

Basic feature of AXI VIP when AXI master VIP is in active mode. AXI pass-through VIP is in passive mode. AXI slave VIP is in active mode with memory model.

sim_basic_mst_active_pt_passive_slv_comb

mst_stimulus.sv

slv_basic_stimulus.sv

generic_tb.sv

Basic feature of AXI VIP when AXI master VIP is in active mode. AXI pass-through VIP is in passive mode AXI slave VIP is in active mode without memory model.

sim_adv_mst_passive_pt_mst_slv_comb

passthrough_mst_stimulus.sv

slv_stimulus.sv

generic_tb.sv

Advanced feature of AXI VIP when AXI master VIP is in passive mode. AXI pass-through VIP is in runtime master mode and talks to AXI slave VIP which does not include memory model.

sim_adv_mst_active_pt_slv_slv_passive

mst_stimulus.sv

passthrough_slv_stimulus.sv

generic_tb.sv

Advanced feature of AXI VIP when AXI master VIP is in active mode. AXI pass-through VIP is in runtime slave mode without memory model. AXI slave VIP is in passive mode.

sim_adv_mst_active_pt_mem_slv_passive

mst_stimulus.sv

passthrough_mem_stimulus.sv

generic_tb.sv

Advanced feature of AXI VIP when AXI master VIP is in active mode. AXI pass-through VIP is in runtime slave mode with memory model. AXI slave VIP in passive mode.

sim_adv_mst_active_pt_passive_slv_mem

mst_stimulus.sv

mem_stimulus.sv

generic_tb.sv

Advanced feature of AXI VIP when AXI master VIP is in active mode. AXI pass-through VIP is in passive mode. AXI slave VIP is in active mode with memory model.

sim_adv_mst_active_pt_passive_slv_comb

mst_stimulus.sv

slv_stimulus.sv

generic_tb.sv

Advanced feature of AXI VIP when AXI master VIP is in active mode. AXI pass-through VIP is in passive mode. AXI slave VIP is in active mode without memory model.

sim_all_config

Shows all of the configured examples.

sim_ready_gen

Usage about ready signal generation with different ready policy and randomization policy.

sim_memory

Usage about memory model such as backdoor_memory_write/read and pre_load_mem.

This Figure to This Figure show the basic, advanced, and all configured simulation sets for AXI VIP .

Figure 6-1: Basic Simulation Sets

X-Ref Target - Figure 6-1

X18985-axi-vip-tb-bsc-simsets.jpg
Figure 6-2: Advanced Simulation Sets

X-Ref Target - Figure 6-2

X18986-axi-vip-tb-adv-simsets.jpg

Figure 6-3: All Configured Simulation Set

X-Ref Target - Figure 6-3

X18988-axi-vip-tb-sim-all-config.jpg

This Figure shows a simulation configuration example in Vivado IDE.

Figure 6-4: Simulation Configuration in Vivado Design Suite

X-Ref Target - Figure 6-4

axi-vip-sim-set.png