Overview - 1.1 English

AXI Verification IP LogiCORE IP Product Guide (PG267)

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1.1 English

This Figure shows the AXI VIP example design.

Figure 5-1: AXI VIP Example Design

X-Ref Target - Figure 5-1


This section describes the example tests used to demonstrate the abilities of the AXI VIP core. Example tests are delivered in SystemVerilog.

When the core example design is open, the example files are delivered in a standard path test bench and bd design are under directory imports. The packages are under the directory example.srcs/sources_1/bd/ex_sim/ipshared .

The example design consists of three components:

AXI VIP in master mode

AXI VIP in pass-through mode

AXI VIP in slave mode

The AXI master VIP creates write/read transactions and sends them to the AXI pass-through VIP. The AXI pass-through VIP receives transactions from the AXI master VIP and sends them to the AXI slave VIP. The AXI slave VIP receives transactions from the AXI pass-through VIP, generates write/read responses, and sends the responses back to the AXI pass-through VIP and then back to AXI master VIP.

Monitors for the AXI VIP (master, pass-through, and slave) are always on and collect all of the information from the interfaces. The monitors convert the interface information back to the transaction level and sends it to the scoreboard. Two scoreboards are built in the test bench which performs self-checking for the AXI master VIP against the AXI pass-through VIP and the AXI slave VIP against the AXI pass-through VIP.

The AXI VIP core is not fully autonomous. If tests are written using the APIs, there are different methods from the user environment to set up the transaction. It is possible that the AXI protocol can be accidentally violated. The member functions of the transaction class performs quick protocol and configuration checks. Xilinx recommends the use of transaction randomization and constraints for generating generic transactions. Furthermore, it is possible to further modify a transaction after it was originally generated through a randomization.

When the AXI VIP is configured in pass-through mode, it has the ability to be a passive monitor or it can take control of the interface. The AXI VIP can change to be a master driving a downstream slave or a slave responding to the master. This process can be done during a simulation at any time and then changed back to pass-through mode according to your preference.

When it is switched to runtime master mode, it behaves exactly as an AXI master VIP. When it is switched to runtime slave mode, it behaves exactly as an AXI slave VIP.

IMPORTANT: Ensure all transactions have completed before switching modes. Examples of how to wait for the transactions to finish can be found in the example design.