Signal Name
|
I/O
|
AXI4
|
AXI3
|
AXI4-LITE
|
Width
|
Description
|
Enablement
|
m_axi_awid
|
O
|
x
|
x
|
|
ID_WIDTH
|
Write Address Channel Transaction ID
|
ID_WIDTH > 0
|
m_axi_awaddr
|
O
|
x
|
x
|
x
|
ADDR_
WIDTH
|
Write Address Channel Transaction Address (12-64)
|
|
m_axi_awlen
|
O
|
x
|
x
|
|
8 for AXI4
4 for AXI3
|
Write Address Channel Transaction Burst Length (0-255)
|
|
m_axi_awsize
|
O
|
x
|
x
|
|
3
|
Write Address Channel Transfer Size Code (0-7)
|
Always ON when it is in AXI3/AXI4
|
m_axi_awburst
|
O
|
x
|
x
|
|
2
|
Write Address Channel Burst Type Code (0-2)
|
HAS_BURST == 1
|
m_axi_awlock
|
O
|
x
|
x
|
|
2 for AXI4
1 for AXI3
|
Write Address Channel Atomic Access Type (0-1)
|
HAS_LOCK == 1
|
m_axi_awcache
|
O
|
x
|
x
|
|
4
|
Write Address Channel Cache Characteristics
|
HAS_CACHE == 1
|
m_axi_awprot
|
O
|
x
|
x
|
x
|
3
|
Write Address Channel Protection Characteristics
|
HAS_PROT == 1
|
m_axi_awqos
|
O
|
x
|
|
|
4
|
Write Address Channel Quality of Service
|
HAS_QOS == 1
|
m_axi_awregion
|
O
|
x
|
|
|
4
|
Write Address Channel Region Index
|
HAS_REGION== 1
|
m_axi_awuser
|
O
|
x
|
|
|
AWUSER_
WIDTH
|
Write Address Channel User-defined signals
|
AWUSER_
WIDTH > 0
|
m_axi_awvalid
|
O
|
x
|
x
|
x
|
1
|
Write Address Channel Valid
|
|
m_axi_awready
|
I
|
x
|
x
|
x
|
1
|
Write Address Channel Ready
|
|
m_axi_arid
|
O
|
x
|
x
|
|
ID_WIDTH
|
Read Address Channel Transaction ID
|
ID_WIDTH > 0
|
m_axi_araddr
|
O
|
x
|
x
|
x
|
ADDR_
WIDTH
|
Read Address Channel Transaction Address (12-64)
|
|
m_axi_arlen
|
O
|
x
|
x
|
|
8 for AXI4
4 for AXI3
|
Read Address Channel Transaction Burst Length (0-255)
|
Always ON when it is AXI3/AXI4
|
m_axi_arsize
|
O
|
x
|
x
|
|
3
|
Read Address Channel Transfer Size Code (0-7)
|
Always ON when it is in AXI3/AXI4
|
m_axi_arburst
|
O
|
x
|
x
|
|
2
|
Read Address Channel Burst Type Code (0-2)
|
HAS_BURST == 1
|
m_axi_arlock
|
O
|
x
|
x
|
|
2 for AXI4
1 for AXI3
|
Read Address Channel Atomic Access Type (0-1)
|
HAS_LOCK == 1
|
m_axi_arcache
|
O
|
x
|
x
|
|
4
|
Read Address Channel Cache Characteristics
|
HAS_CACHE == 1
|
m_axi_arprot
|
O
|
x
|
x
|
x
|
3
|
Read Address Channel Protection Characteristics
|
HAS_PROT == 1
|
m_axi_arqos
|
O
|
x
|
|
|
4
|
Read Address Channel Quality of Service
|
HAS_QOS == 1
|
m_axi_arregion
|
O
|
x
|
|
|
4
|
Read Address Channel Region Index
|
HAS_REGION == 1
|
m_axi_aruser
|
O
|
x
|
|
|
ARUSER_
WIDTH
|
Read Address Channel User-defined signals.
|
AWUSER_
WIDTH > 0
|
m_axi_arvalid
|
O
|
x
|
x
|
x
|
1
|
Read Address Channel Valid
|
|
m_axi_arready
|
I
|
x
|
x
|
x
|
1
|
Read Address Channel Ready
|
|
m_axi_wid
|
O
|
|
x
|
|
ID_WIDTH
|
|
ID_WIDTH > 0
|
m_axi_wlast
|
O
|
x
|
x
|
|
1
|
Write Data Channel Last Data Beat
|
|
m_axi_wdata
|
O
|
x
|
x
|
x
|
DATA_
WIDTH
|
Write Data Channel Data
|
|
m_axi_wstrb
|
O
|
x
|
x
|
x
|
DATA_
WIDTH/8
|
Write Data Channel Byte Strobes
|
HAS_WSTRB == 1
|
m_axi_wuser
|
O
|
x
|
x
|
|
WUSER_
WIDTH
|
Write Data Channel user-defined signal
|
WUSER_WIDTH > 0
|
m_axi_wvalid
|
O
|
x
|
x
|
x
|
1
|
Write Data Channel Valid
|
|
m_axi_wready
|
I
|
x
|
x
|
x
|
1
|
Write Data Channel Ready
|
|
m_axi_rid
|
I
|
x
|
|
|
ID_WIDTH
|
Read Data Channel Transaction ID
|
ID_WIDTH > 0
|
m_axi_rlast
|
I
|
x
|
|
|
1
|
Read Data Channel Last Data Beat
|
|
m_axi_rdata
|
I
|
x
|
|
x
|
DATA_
WIDTH
|
Read Data Channel Data
|
|
m_axi_rresp
|
I
|
x
|
|
x
|
2
|
Read Data Channel Response Code (0-3)
|
HAS_RRESP == 1
|
m_axi_ruser
|
I
|
x
|
|
|
RUSER_
WIDTH
|
Read Data Channel user-defined signal
|
RUSER_WIDTH> 0
|
m_axi_rvalid
|
I
|
x
|
|
x
|
1
|
Read Data Channel Valid
|
|
m_axi_rready
|
O
|
x
|
|
x
|
1
|
Read Data Channel Ready
|
|
m_axi_bid
|
I
|
x
|
|
|
ID_WIDTH
|
Write Response Channel Transaction ID
|
ID_WIDTH > 0
|
m_axi_bresp
|
I
|
x
|
|
x
|
2
|
Write Response Channel Response Code (0-3)
|
HAS_BRESP > 0
|
m_axi_buser
|
I
|
x
|
|
|
BUSER_
WIDTH
|
Write Response Channel user-defined signal
|
BUSER_WIDTH> 0
|
m_axi_bvalid
|
I
|
x
|
|
x
|
1
|
Write Response Channel Valid
|
|
m_axi_bready
|
O
|
x
|
|
x
|
1
|
Write Response Channel Ready
|
|