The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
12/02/2021 |
1.1 |
• Updated Table: AXI Master or Pass-Through VIP Port Descriptions and Table: AXI Slave or Pass-Through VIP Port Descriptions . • Updated Finding the AXI VIP Hierarchy Path in IP Integrator section. • Updated API documentation link in References . |
|
10/30/2019 |
1.1 |
Updated API documentation link in References . |
|
05/22/2019 |
1.1 |
• Added sim_ready_gen and sim_memory in Table: Simulation Sets for AXI VIP . • Updated This Figure . • Updated API documentation link in References . |
|
12/05/2018 |
1.1 |
• Updated backdoor_memory_write and backdoor_memory_read arrows for This Figure . • Updated Finding the AXI VIP Hierarchy Path in IP Integrator section. • Corrected generic_tb file name and added description to modes in Multiple Simulation Sets . • Updated GEN_RANDOM heading in AXI VIP Agent and Flow Methodology . |
|
04/04/2018 |
1.1 |
Updated to latest Vivado Design Suite. |
|
12/20/2017 |
1.1 |
• Updated NARROW description in Product Specification chapter.. • Added Issue Capability section in Test Bench chapter. |
|
10/04/2017 |
1.1 |
• Added Note #6 in IP Facts table. • Updated SUPPORTS_NARROW, HAS_LOCK, HAS_WSTRB, HAS_BRESP, and HAS_RRESP descriptions in AXI VIP User Parameters table. • Added ARESET_XCHECK and XILINX_AXI_ERRM_RESET_PULSE_WIDTH in Xilinx Configuration Checks and Descriptions table. • Updated Arm reference 1. • Updated Overview section in Example Design chapter. • Updated code in Create Ready Signal section in Test Bench chapter. • Updated Must Haves section and added Reactive Ports for the AXI Slave VIP section in the Test Bench chapter. • Added GEN_NO_BACKPRESSURE section to Configurable Ready Delays section. • Added APIs to axi_vip_v1_1_top APIs appendix. |
|
06/07/2017 |
1.0 |
• Added note #5-7 in IP Facts table. • Added description in Multiple Simulation Sets section in Test Bench chapter. • Added type definition description in AXI Pass-Through VIP section in Test Bench chapter. |
|
04/05/2017 |
1.0 |
Initial Xilinx release. |