The following table shows the revision history for this document:
| Section | Revision Summary |
|---|---|
| 05/16/2023 Version 1.1 | |
| General updates |
Updated design file. Editorial updates only. No technical content updates. |
| 12/02/2021 Version 1.1 | |
| Port Descriptions | Updated Table 2 and Table 4. |
| Finding the AXI VIP Hierarchy Path in IP Integrator | Updated Finding the AXI VIP Hierarchy Path in IP integrator section. |
| References | Updated API documentation link in References. |
| 05/22/2019 Version 1.1 | |
| Mode Transaction Generation | Added sim_ready_gen and sim_memory in Table 6-1. |
| Mode Transaction Generation | Updated Figure 24. |
| References | Updated API documentation link in References. |
| 12/05/2018 Version 1.1 | |
| Simple SRAM Memory Model | Updated backdoor_memory_write and backdoor_memory_read arrows for Figure 4-8. |
| Finding the AXI VIP Hierarchy Path in IP Integrator | Updated Finding the AXI VIP Hierarchy Path in IP Integrator section. |
| Mode Transaction Generation | Corrected generic_tb file name and added description to modes in Multiple Simulation Sets. |
| AXI VIP Agent and Flow Methodology | Updated GEN_RANDOM heading in AXI VIP Agent and Flow Methodology. |
| 04/04/2018 Version 1.1 | |
| Upgrading | Updated to latest Vivado Design Suite. |
| 12/20/2017 Version 1.0 | |
| Product Specification | Updated NARROW description in Product Specification chapter. |
| Test Bench | Added Issue Capability section in Test Bench chapter. |
| 10/04/2017 Version 1.1 | |
| IP Facts | Added Note #6 in IP Facts table. |
| User Parameters | Updated SUPPORTS_NARROW, HAS_LOCK, HAS_WSTRB, HAS_BRESP, and HAS_RRESP descriptions in AXI VIP User Parameters table. |
| AMD Configuration Checks and Descriptions | Added ARESET_XCHECK and XILINX_AXI_ERRM_RESET_PULSE_WIDTH in Xilinx Configuration Checks and Descriptions table. |
| References | Updated Arm reference 1. |
| Overview | Updated Overview section in Example Design chapter. |
| Create Ready Signal | Updated code in Create Ready Signal section in Test Bench chapter. |
| Test Bench | Updated Must Haves section and added Reactive Ports for the AXI Slave VIP section in the Test Bench chapter. |
| Configurable Ready Delays | Added GEN_NO_BACKPRESSURE section to Configurable Ready Delays section. |
| axi_vip_v1_1_top APIs | Added APIs to axi_vip_v1_1_top APIs appendix. |
| 06/07/2017 Version 1.0 | |
| IP Facts | Added note #5-7 in IP Facts table. |
| Mode Transaction Generation | Added description in Multiple Simulation Sets section in Test Bench chapter. |
| AXI Pass-Through VIP | Added type definition description in AXI Pass-Through VIP section in Test Bench chapter. |
| 04/05/2017 Version 1.0 | |
| Initial release. | N/A |