Table: Xilinx Configuration Checks and Descriptions lists the Xilinx configuration checks and descriptions.
Name of Protocol Check |
Protocol Support |
Description |
---|---|---|
XILINX_AW_SUPPORTS_NARROW_BURST |
AXI4/AXI3 |
When the connection does not support narrow transfers, the AW Master cannot issue a transfer with AWLEN > 0 and AWSIZE less than the defined interface DATA_WIDTH. |
XILINX_AR_SUPPORTS_NARROW_BURST |
AXI4/AXI3 |
When the connection does not support narrow transfers, the AR Master cannot issue a transfer with ARLEN > 0 and ARSIZE less than the defined interface DATA_WIDTH. |
XILINX_AW_SUPPORTS_NARROW_CACHE |
AXI4/AXI3 |
When the connection does not support narrow transfers, the AW Master cannot issue a transfer with AWLEN > 0 and AWCACHE modifiable bit not asserted. |
XILINX_AR_SUPPORTS_NARROW_CACHE |
AXI4/AXI3 |
When the connection does not support narrow transfers, the AR Master cannot issue a transfer with ARLEN > 0 and ARCACHE modifiable bit not asserted. |
XILINX_AW_MAX_BURST |
AXI4/AXI3 |
AW Master cannot issue AWLEN greater than the configured maximum burst length. |
XILINX_AR_MAX_BURST |
AXI4/AXI3 |
AR Master cannot issue ARLEN greater than the configured maximum burst length. |
XILINX_AWVALID_RESET |
AXI4/AXI3/Lite |
AWREADY is Low for the first cycle after ARESETn goes High. |
XILINX _WVALID_RESET |
AXI4/AXI3/Lite |
WREADY is Low for the first cycle after ARESETn goes High. |
XILINX _BVALID_RESET |
AXI4/AXI3/Lite |
BREADY is Low for the first cycle after ARESETn goes High. |
XILINX _ARVALID_RESET |
AXI4/AXI3/Lite |
ARREADY is Low for the first cycle after ARESETn goes High. |
XILINX _RVALID_RESET |
AXI4/AXI3/Lite |
RREADY is Low for the first cycle after ARESETn goes High. |
ARESET_XCHECK |
AXI4/AXI3/Lite |
AREST_N cannot be X/Z after one clock cycle. |
XILINX_AXI_ERRM_RESET_PULSE_WIDTH |
AXI4/AXI3/Lite |
ARESETN must stay at least 16 clock cycles long when it goes Low. For more information, see the Vivado Design Suite User Guide: AXI Reference Guide (UG1037) [Ref 3] . |