This register contains the counter defining the delay from a fatal error has been detected until the MicroBlaze break signal is set to 1. The register definition is shown in Table: Break Delay Initialization Register (BDIR) . The register is write-only. Issuing a read request generates the read acknowledgment with zero data. The register is only implemented if C_BRK_DELAY_WIDTH is greater than 0, and the initial value after reset is determined by C_BRK_DELAY_RST_VALUE.