First Failing Register (FFR) - 1.0 English

MicroBlaze Triple Modular Redundancy (TMR) Subsystem (PG268)

Document ID
PG268
Release Date
2022-04-28
Version
1.0 English

The first failing register contains the TMR subsystem fault status. This is a read/write register. Issuing a write request to the first failing register with any data clears the entire register, provided that the MAGIC1 field in the Control Register is correctly set. The register bit assignment is shown in Table: First Failing Register (FFR) and described in Table:  First Failing Register Bit Definitions .

Table 2-30: First Failing Register (FFR)

Reserved

WE

FAT
UE

FAT
V

FAT
23

FAT
13

FAT
12

Reserved

REC

LM
23

LM
13

LM12

31

22

21

20

19

18

17

16

15

4

3

2

0

0

Table 2-31: First Failing Register Bit Definitions

Bits

Name

Access

Reset
Value

Description

31-22

Reserved

N/A

0

Reserved

21

Watchdog Expired

R/W

0

Indicates if the watchdog has expired:

0 - The watchdog has not expired.
1 - The watchdog has expired.

20

Fatal Uncorrectable Error

R/W

0

Fatal ECC uncorrectable error has occurred:

0 = No fatal error.
1 = A fatal error has occurred.

19

Fatal Voter Error

R/W

0

Fatal voter error has occurred:

0 = No fatal error.
1 = A fatal error has occurred.

18

Fatal 2-3

R/W

0

Fatal error has occurred for processors 2 and 3 causing transition to Fatal state:

0 = No fatal error.
1 = A fatal error has occurred.

17

Fatal 1-3

R/W

0

Fatal error has occurred for processors 1 and 3 causing transition to Fatal state:

0 = No fatal error.
1 = A fatal error has occurred.

16

Fatal 1-2

R/W

0

Fatal error has occurred for processors 1 and 2 causing transition to Fatal state:

0 = No fatal error.
1 = A fatal error has occurred.

15-4

Reserved

N/A

0

Reserved

3

Recovery

R/W

0

Indicates if a recovery has been performed:
0 = No recovery.
1 = A recovery has occurred.

2 (1)

Lockstep mismatch 2-3

R/W

0

Lockstep mismatch between processor 2 and 3 causing transition to Lockstep state:

0 = No lockstep mismatch.
1 = Lockstep mismatch has occurred.

1 (1)

Lockstep mismatch 1-3

R/W

0

Lockstep mismatch between processor 1 and 3 causing transition to Lockstep state:

0 = No lockstep mismatch.
1 = Lockstep mismatch has occurred.

0 (1)

Lockstep mismatch 1-2

R/W

0

Lockstep mismatch between processor 1 and 2 causing transition to Lockstep state:

0 = No lockstep mismatch.
1 = Lockstep mismatch has occurred.

Notes:

1. The Lockstep mismatch bits indicate which processors have detected a mismatch, and if one processor is faulty the two others will detect a mismatch. Consequently, two of the three bits will be set when one processor can be identified as faulty. For example, if processor 1 is faulty, both processors 2 and 3 will detect a mismatch, and the bits will have the binary value 011. In case only one or all three of the bits are set, the processors do not agree on which one is faulty, and recovery is not possible.